1. Field of the Invention
The present invention relates to the fabrication and use of integrated circuits. More particularly, the present invention relates to the mapping of a matrix of functional integrated circuits formed on a semiconductor wafer substrate.
2. Description of the Prior Art
Several techniques have been developed to increase circuit integration by interconnection of functional circuits on a wafer containing a matrix of functional and non-functional circuits. One such technique, referred to as "discretionary wiring", includes individual testing of circuits formed on the wafer, mapping of functional circuits, and formation under computer control of unique metal interconnections for that particular wafer. A mask is used to form a unique metal interconnecting layer that interconnects only the functional circuits. Disadvantages of this technique include the cost of producing a custom mask for each individual wafer and the requirement of a subsequent metallization step that may introduce additional defects, making the wafer completely nonfunctional. As a result, the cost and effort of making the wafer and of generating the custom mask, which is only useful in conjunction with that particular wafer is wasted.
Another technique for increasing circuit integration is disclosed by Russell, et al. in U.S. Pat. No. 4,122,540, issued Oct. 24, 1978 and assigned to Signetics Corporation of Sunnyvale, Calif. The Russell, et al. technique consists of making individual circuits with interconnecting leads and arranging the circuits along an interconnecting grid. Individual circuits are connected to or disconnected from the interconnecting grid according to the circuit's functionality. In contrast to "discretionary wiring", this technique does not require additional processing steps. However, an orthogonal interconnecting grid must be provided on two layers of materials. That is, at least two layers of metal or connect planes are needed for the grid's horizontal and vertical lead lines.
Another disadvantage of the Russell, et al. technique is that a limit is placed on the use of individual functional circuits. Because the circuits are wired in a predetermined manner, ultralarge scale integration may not be complete if there are less than the required number of functional circuits available along a grid line. For example, in a 14.times.14 matrix of 196 circuits that when integrated yields a 9.times.8 matrix of 72 functional circuits, it is possible that the 72 required functional circuits may not fall at the required locations on the grid. That is, the 72 functional circuits may be distributed so that they do not make a 9.times.8 matrix. Thus, the final product may not be a working product having a 9.times.8 matrix.
The Russell, et al. technique requires significantly more than the required number of functional circuits. For example, 100 functional circuits may be required to form a 9.times.8 matrix of 72 functional circuits. This is due to the imposition of a wiring grid and lack of flexibility of subsequent wiring (after testing). Russell, et al. eliminates the subsequent metallization step and custom metal mask required by "discretionary wiring" by "wasting" functional circuits.
Another problem with the Russell, et al. technique is the difficulty of testing individual circuits in the presence of the interconnecting grid. To adequately test these circuits without one interfering with results obtained for another, the interconnecting grid must be disconnected from the circuit being tested. The interconnecting grid must thereafter become very low impedance after programming.
Another technique for wafer level integration is given by Chesley in U.S. Pat. No. 4,038,648, issued July 26, 1977. Chesley provides for bypassing non-functional bits of a device through the use of electrical latches. Such technique requires resetting the latches each time the device is powered up. Accordingly, an additional diagnostic and test program is required to reset the latches on power up. Such technique is generally not practical and has the further disadvantage in that the individual circuits are not physically isolated for testing.